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integrated silicon solution, inc. ? 1-800-379-4774 1 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 2k-bit/4k-bit spi serial electrically erasable prom features ? serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) ? low-voltage operation ? vcc = 1.8v to 5.5v ? low power cmos ? active current less than 3.0 ma (2.5v) ? standby current less than 1 a (2.5v) ? block write protection ? protect 1/4, 1/2, or entire array ? 16 byte page write mode ? partial page writes allowed ? 10 mhz clock rate (5v) ? self timed write cycles ? 5 ms max. @ 2.5v ? high-reliability ? endurance: 1 million cycles per byte ? data retention: 100 years ? 8-pin pdip, 8-pin soic, and 8-pin tssop packages are available ? lead-free available preliminary information january 2006 the IS25C02 and is25c04 are electrically erasable prom devices that use the serial peripheral interface (spi) for communications. the IS25C02 is 2kbit (256x 8) and the is25c04 is 4kbit (512x 8). the IS25C02/04 eeproms are offered in a wide operating voltage range of 1.8v to 5.5v to be compatible with most application voltages. issi designed the IS25C02/ 04 to be an efficient spi eeprom solution. the devices are packaged in 8-pin pdip, 8-pin soic, and 8- pin tssop. the functional features of the IS25C02/04 allow them to be among the most advanced serial non-volatile memo- ries available. each device has a chip-select ( cs ) pin, and a 3-wire interface of serial data in (si), serial data out (so), and serial clock (sck). while the 3-wire interface of the IS25C02/04 provides for high-speed access, a hold pin allows the memories to ignore the interface in a suspended state; later the hold pin re- activates communication without re-initializing the serial sequence. a status register facilitates a flexible write protection mechanism, and a device-ready bit ( rdy ). description
2 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? write protect ( wp wp wp wp wp ): the purpose of this input signal is to initiate hardware write protection mode. this mode prevents the 256/512 byte array or the status register from being altered. to cause hardware write protection, wp must be low. wp may be hardwired to vcc or gnd. hold ( hold hold hold hold hold ): this input signal is used to suspend the device in the middle of a serial sequence and temporarily ignore further communication on the bus (si, so, sck). together with chip select, the hold signal allows multiple slaves to share the bus. the hold signal transitions must occur only when sck is low, and be held stable during sck transitions. (see figure 8 for hold timing) to disable this feature, hold may be hardwired to vcc. pin descriptions cs chip select sck serial data clock si serial data input so serial data output gnd ground v cc power wp write protect hold suspends serial input pin descriptions serial clock (sck): this timing signal provides syn- chronization between the microcontroller and IS25C02/ 04. op-codes, byte addresses, and data are latched on si with a rising edge of the sck. data on so is re- freshed on the falling edge of sck for spi modes (0,0) and (1,1). serial data input (si): this is the input pin for all data that the IS25C02/04 is required to receive. serial data output (so): this is the output pin for all data transmitted from the IS25C02/04. pin configuration 8-pin dip, soic, and tssop chip select ( cs cs cs cs cs ): the cs pin activates the device. upon power-up, cs should follow vcc. when the device is to be enabled for instruction input, the signal requires a high-to-low transition. while cs is stable low, the master and slave will communicate via sck, si, and so signals. upon completion of communication, cs must be driven high. at this moment, the slave device may start its internal write cycle. when cs is high, the device enters a power-saving standby mode, unless an internal write operation is underway. during this mode, the so pin becomes high impedance. 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si
integrated silicon solution, inc. ? 1-800-379-4774 3 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? serial interface description master: the device that provides a clock signal. slave: the IS25C02/04 is a slave because the clock signal is an input. transmitter/receiver: the IS25C02/04 has both data input (si) and data output (so). msb: the most significant bit. it is always the first bit transmitted or received. op-code: the first byte transmitted to the slave following cs transition to low. if the op-code is a valid member of the IS25C02/04 instruction set (table 3), then it is decoded appropriately. if the op-code is not valid, and the so pin remains in high impedance. block diagram status register 256 x 8/512 x 8 memory array hold cs wp clock so output buffer sck si data register mode decode logic gnd vcc address decoder
4 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? status register table 1. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 x xxx bp1bp0wen rdy the status register contains 8-bits for write protection control and write status. (see table 1). it is the only region of memory other than the main array that is accessible by the user. the status register is read-only if either: a) hardware write protection is enabled or b) wen is set to 0. if neither is true, it can be modified by a valid instruction. ready ( rdy rdy rdy rdy rdy ), bit 0: when rdy = 1, it indicates that the device is busy with a write cycle. rdy = 0 indi- cates that the device is ready for an instruction. if rdy = 1, the only command that will be handled by the device is read status register. don?t care, bits 4-7: each of these bits can receive either 0 or 1, but values will not be retained. when these bits are read from the register, they are always 0. notes: 1. x = don't care bit. 2. during internal write cycles, bits 0 to 7 are temporarily 1's. block protect (bp1, bp0), bits 2-3: together, these bits represent one of four block protection configurations implemented for the memory array. (see table 2 for details.) bp0 and bp1 are non-volatile cells similar to regular array cells, and factory programmed to 0. the block of memory defined by these bits is always protected, regardless of the setting of wp or wen. table 2. block protection status register bits array addresses protected level bp1 bp0 i s25c02 is25c04 0 0 0 none none 1(1/4) 0 1 c0h 180h -ffh -1ffh 2(1/2) 1 0 80h 100h -ffh -1ffh 3(all) 1 1 00h 000h -ffh -1ffh write enable (wen), bit 1: this bit represents the status of device write protection. if wen = 0, the status register and the entire array is protected from modifica- tion, regardless of the setting of wp pin or block protec- tion. the only way to set wen to 1 is via the write enable command (wren). wen is reset to 0 upon power-up, successful completion of write, wrdi, wrsr, or wp being low.
integrated silicon solution, inc. ? 1-800-379-4774 5 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? write enable (wren) when vcc is initially applied, the device powers up with both status register and entire array in a write-disabled state. upon completion of write disable (wrdi), write status register (wrsr), or write data to array (write), the device resets the wen bit in the status register to 0. prior to any data modification, a wren instruction is necessary to set wen to 1. (see figure 2 for timing). write disable (wrdi) the device can be completely protected from modifica- tion by resetting wen to 0 through the wrdi instruc- tion. (see figure 3 for timing). read status register (rdsr) the read status instruction indicates the status of the block protection setting (see table 2), the write enable state, and the rdy status. rdsr is the only instruc- tion accepted when a write cycle is underway. it is recommended that the status of rdy be checked, especially prior to an attempted modification of data. the 8 bits of the status register can be repeatedly output on so after the initial op-code. (see figure 4 for timing). table 3. instruction set name op-code operation address data(si) data (so) wren 0000 x110 set write enable latch - -- wrdi 0000 x100 reset write enable latch - - - rdsr 0000 x101 read status register - - d 7 -d 0 ,... wrsr 0000 x001 write status register - d 7 -d 0 - read 0000 a 8 011 read data from array a 7 -a 0 -d 7 -d 0 ,... write 0000 a 8 010 write data to array a 7 -a 0 d 7 -d 0 ,... - device operation the operations of the IS25C02/04 are controlled by a set of instructions that are clocked-in serially si pin. (see table 3). to begin an instruction, the chip select ( cs ) should be dropped low. subsequently, each low-to-high transition of the clock (sk) will latch a stable value on the si pin. after the 8-bit op-code, it may be appropriate to continue to input an address or data to si, or to output data from so. during data output, values appear on the falling edge of sk. all bits are transferred with msb first. upon the last bit of communication, but prior to any following low-to-high transition of sk, cs should be raised high to end the transaction. the device then would enter standby mode if no internal programming were underway. 1. x = don?t care bit. for consistency, it is best to use ?0?. 2. some address bits are don?t care. see table 5. 3. if the bits clocked-in for an op-code are invalid, so remains high impedance, and upon cs going high there is no affect. a valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or status register to be ignored.
6 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? table 5. address key name IS25C02 is25c04 a n a 7- a 0 a 8- a 0 don't a 8 - care bits write status register (wrsr) this instruction lets the user choose a block protection setting. the values of the other data bits incorporated into wrsr can be 0 or 1, and are not stored in the status register. wrsr will be ignored unless both the following are true: a) wen = 1, due to a prior wren instruction; and b) hardware write protection is not enabled. (see table 4 for details). except for the rdy status, the values in the status register remain un- changed until the moment when the write cycle is complete and the register is updated. once successfully completed, wen is reset for complete chip write protec- tion. (see figure 5 for timing). read data (read) this instruction begins with the op-code and the 8-bit address, and causes the selected data byte to be shifted out on so. following this first data byte, addi- tional sequential bytes are output. if the data byte in the highest address is output, the address rolls-over to the lowest address in the array, and the output could loop indefinitely. at any time, a rising cs signal completes the operation. (see figure 6 for timing). write data (write) the write instruction begins with the op-code, the 8-bit address of the first byte to be modified, and the first data byte. additional data bytes may be written sequentially to the array after the first byte. each write instruction can affect the contents of a 16 byte page, but no more. the page begins at address xxxx 0000, and ends with xxxx 1111. if the last byte of the page is input, the address rolls over to the beginning of the same page. more than 16 data bytes can be input during the same instruction, but upon a completed write cycle, a page would only contain the last 16 bytes. the region of the array defined within block protection cannot be modified as long as that block configuration is selected. the region of the array outside the block protection can only be modified if write enable (wen) is set to 1. therefore, it may be necessary that a wren instruction occur prior to write. in addition, if hardware write protection is enabled, the memory array cannot be modified. once write is successfully completed, wen is reset for complete chip write protection. (see figure 7 for timing). table 4. write protection wp wp wp wp wp hardware write wen inside bl ock outside bl ock status register protection 0 enabled x read-only read-only read-only 1 not enabled 0 read-only read-only read-only 1 not enabled 1 read-only unprotected unprotected note: x = don't care bit.
integrated silicon solution, inc. ? 1-800-379-4774 7 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? absolute maximum ratings (1) symbol parameter value unit v s supply voltage -0.5 to + 6.5 v v p voltage on any pin ?0.5 to vcc + 0.5 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c i out output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (is25c04-2 and IS25C02-2) range ambient temperature v cc industrial ?40c to +85c 1.8v to 5.5v note: issi offers industrial grade for commercial applications (0 o c to +70 o c). capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. test conditions: t a = 25c, f = 1 mhz, vcc = 5.0v. operating range (is25c04-3 and IS25C02-3) range ambient temperature v cc automotive ?40c to +125c 2.5v to 5.5v
8 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? dc electrical characteristics t a = ?40c to +85c for industrial, t a = ?40c to +125c for automotive. symbol parameter test conditions min. max. unit v ol 1 output low voltage v cc = 5v, i ol = 2 ma ? 0.4 v v ol 2 output low voltage v cc = 2.5v, i ol = 1.5 ma ? 0.4 v v ol 3 output low voltage v cc = 1.8v, i ol = 0.15 ma ? 0.2 v v o h1 output high voltage v cc = 5v, i oh = -2 ma 0.8 x v cc ?v v o h2 output high voltage v cc = 2.5v, i oh = -0.4ma 0.8 x v cc ?v v o h3 output high voltage v cc = 1.8v, i oh = -0.1ma 0.8 x v cc ?v v ih input high voltage 0.7 x v cc v cc + 1 v v il input low voltage -0.3 0.3 x v cc v i li input leakage current v in = 0v to v cc -2 2 a i lo output leakage current v out = 0v to v cc , cs = v cc -2 2 a power supply characteristics t a = ?40c to +85c for industrial. symbol parameter test conditions min. max. unit i cc 1 vcc operating current read/write at 10 mhz (vcc = 5v) ? 5.0 ma i cc 2 vcc operating current read/write at 5 mhz (vcc = 2.5v) ? 3.0 ma i cc 3 vcc operating current read/write at 2 mhz (vcc = 1.8v) ? 1.0 ma i sb 1 standby current vcc = 5.0v, v in = v cc or gnd ? 2 a cs = vcc i sb 2 standby current vcc = 2.5v, v in = v cc or gnd ? 1 a cs = vcc i sb 3 standby current vcc = 1.8v, v in = v cc or gnd ? 0.5 a cs = vcc power supply characteristics t a = ?40c to +125c for automotive. symbol parameter test conditions min. max. unit i cc 1 vcc operating current read/write at 5 mhz (vcc = 5v) ? 4.0 ma i cc 2 vcc operating current read/write at 5 mhz (vcc = 2.5v) ? 3.0 ma i sb 1 standby current vcc = 5.0v, v in = v cc or gnd ? 5.0 a cs = vcc i sb 2 standby current vcc =2. 5v, v in = v cc or gnd ? 2.0 a cs = vcc
integrated silicon solution, inc. ? 1-800-379-4774 9 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? ac characteristics t a = ?40c to +85c for industrial. 1.8v vcc < 2.5v 2.5v vcc < 4.5v 4.5v vcc 5.5v symbol parameter min max min max min max units f sck sck clock frequency 0 2 0 5 0 10 mhz t ri input rise time ? 2 ? 2 ? 2 s t fi input fall time ? 2 ? 2 ? 2 s t wh sck high time 200 ? 90 ? 40 ? ns t wl sck low time 200 ? 90 ? 40 ? ns t cs cs high time 200 ? 100 ? 40 ? ns t css cs setup time 200 ? 90 ? 40 ? ns t csh cs hold time 200 ? 90 ? 25 ? ns t su data in setup time 40 ? 20 ? 15 ? ns t h data in hold time 50 ? 30 ? 15 ? ns t hd hold setup time 100 ? 50 ? 25 ? ns t cd hold hold time 100 ? 50 ? 25 ? ns t v output valid 0 150 0 60 0 25 ns t ho output hold time 0 ? 0 ? 0 ? ns t lz hold to output low z 0 100 0 50 0 25 ns t hz hold to output high z ? 250 ? 100 ? 25 ns t dis output disable time ? 250 ? 100 ? 25 ns t wc write cycle time ? 10 ? 5 ? 5 ms c l = 100pf
10 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? ac characteristics t a = ?40c to +125c for automotive. 2.5v vcc < 4.5v 4.5v vcc 5.5v symbol parameter min max min max units f sck sck clock frequency 0 5 0 10 mhz t ri input rise time ? 2 ? 2 s t fi input fall time ? 2 ? 2 s t wh sck high time 90 ? 40 ? ns t wl sck low time 90 ? 40 ? ns t cs cs high time 100 ? 40 ? ns t css cs setup time 90 ? 40 ? ns t csh cs hold time 90 ? 25 ? ns t su data in setup time 20 ? 15 ? ns t h data in hold time 30 ? 15 ? ns t hd hold setup time 50 ? 25 ? ns t cd hold hold time 50 ? 25 ? ns t v output valid 0 60 0 25 ns t ho output hold time 0 ? 0 ? ns t lz hold to output low z 0 50 0 25 ns t hz hold to output high z ? 100 ? 25 ns t dis output disable time ? 100 ? 25 ns t wc write cycle time ? 5 ? 5 ms c l = 100pf
integrated silicon solution, inc. ? 1-800-379-4774 11 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? timing diagrams figure 3. wrdi timing figure 2. wren timing figure 1. synchronous data timing cs sk d in d out v ih v il v ih v il v ih v il v oh v ol valid in high-z high-z t css t wh t wl t h t su t cs t csh t v t ho t dis high-z wren op-code cs sk d in d out high-z wrdi op-code cs sk d in d out
12 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? figure 6. read timing figure 5. wrsr timing figure 4. rdsr timing cs sk din dout instruction 7 6 5 4 3 2 1 0 data out cs sk din dout instruction 7 6 5 4 3 2 1 0 data i n 7 6 5 4 3 2 1 0 cs sk din dout instruction byte address 7 6 5 4 3 2 1 0 data out a8
integrated silicon solution, inc. ? 1-800-379-4774 13 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? figure 8. hold hold hold hold hold timing figure 7. write timing 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 cs sk din dout instruction byte address a8 data i n cs sck hold d out t cd t hd t hz t lz t hd t cd
14 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00f 12/22/05 IS25C02 is25c04 issi ? ordering information industrial range: ?40c to +85c voltage range part number package 1.8v IS25C02-2pi 300-mil plastic dip to 5.5v IS25C02-2gi sm all outline (jedec std) IS25C02-2zi 169-mil tssop 1.8v is25c04-2pi 300-mil plastic dip to 5.5v is25c04-2gi sm all outline (jedec std) is25c04-2zi 169-mil tssop automotive range: ?40c to +125c, lead-free voltage range part number package 2.5v IS25C02-3pla3 300-mil plastic dip to 5.5v IS25C02-3gla3 sm all outline (jedec std) IS25C02-3zla3 169-mil tssop 2.5v is25c04-3pla3 300-mil plastic dip to 5.5v is25c04-3gla3 sm all outline (jedec std) is25c04-3zla3 169-mil tssop industrial range: -40c to +85c, lead-free voltage range part number package 1.8v IS25C02-2pli 300-mil plastic dip to 5.5v IS25C02-2gli sm all outline (jedec std) IS25C02-2zli 169-mil tssop 1.8v is25c04-2pli 300-mil plastic dip to 5.5v is25c04-2gli sm all outline (jedec std) is25c04-2zli 169-mil tssop
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/14/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 300-mil plastic dip package code: n,p a d 1 b n seating plane c a1 e a l e b1 s e1 e s for 32-pin only b2 millimeters inches sym. min. max. min. max. n0. leads 8 a 3.68 4.57 0.145 0.180 a1 0.38 ? 0.015 ? b 0.36 0.56 0.014 0.022 b1 1.14 1.52 0.045 0.060 b2 0.81 1.17 0.032 0.046 c 0.20 0.33 0.008 0.013 d 9.12 9.53 0.359 0.375 e 7.62 8.26 0.300 0.325 e1 6.20 6.60 0.244 0.260 e a 8.13 9.65 0.320 0.380 e 2.54 bsc 0.100 bsc l 3.18 ? 0.125 ? s 0.64 0.762 0.025 0.030 notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
packaging information issi ? integrated silicon solution, inc. ? 1-800-379-4774 2 rev. c 10/03/01 150-mil plastic sop package code: g, gr d seating plane b e c 1 n e a1 a h l notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 150-mil plastic sop (g, gr) symbol min max min max ref. std. inches mm no. leads 8 8 a ? 0.068 ? 1.73 a1 0.004 0.009 0.1 0.23 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.18 0.25 d 0.189 0.197 4.8 5 e 0.150 0.157 3.81 3.99 h 0.228 0.245 5.79 6.22 e 0.050 bsc 1.27 bsc l 0.020 0.035 0.51 0.89
integrated silicon solution, inc. packaging information issi ? thin shrink small outline tssop package code: z (8 pin, 14 pin) rev b 02/01/02 tssop (z) ref. std. jedec mo-153 no. leads 8 millimeters inches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 2.90 3.10 0.114 0.122 e1 4.30 4.50 0.169 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 ?8 ?8 tssop (z) ref. std. jedec mo-153 no. leads 14 millimeters i nches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.10 0.193 0.201 e1 4.30 4.50 0.170 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.0177 0.0295 ?8 ? 8 d b e e1 a2 e c a a1 l 1 n n/2 ssi reserves the right to make changes to its products at any time without notice in order to improve design and supply the bes t possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2002, integrated silicon solution, inc.

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